Typically in the fabrication of semiconductor devices, a plurality of patterned layers are successively formed into a stack on a semiconductor substrate. Photolithography is conventionally used to produce various patterned layers. In photolithography, it is critical that the successive, patterned layers are accurately aligned relative to each other. Presently, it is conventional to use overlay verniers of the box-in-box type to measure the overlay or placement error of the patterns. These overlay verniers are typically formed at the scribe lines on the semiconductor wafer being processed.
FIG. 1 shows the top plan view of a conventional overlay vernier having an inner vernier 2 formed at an upper level and an outer vernier 1 formed at a lower level in a semiconductor device being fabricated. The outer vernier 1 contains four slits 3a, 3b, 3c, 3d, which define a square. The slits 3a, 3b, 3c, 3d are conventionally filled with a suitable insulative or conductive material. The inner vernier 2 is smaller in size than the outer vernier 1 and is positioned over the center of the outer vernier 1 as shown in FIG. 1. The overlay accuracy between the patterned layers is measured by comparing the distances a, b, c, d between the inner vernier 2 and the slits 3a, 3b, 3c, 3d. The outer vernier 1 is typically large in size, thus, it is affected easily by thermal processing and chemical-mechanical polishing during device fabrication. Thermal processing, e.g., baking at a high temperature, may cause the outer vernier 1 to be deformed due to expansion or shrinkage. This deformation results in overlay measurement error.